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1 fn6786.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. d2-81412, D2-81433, d2-81434, d2-81435 dae-1 for manufacturers of high- performance class- d audio amplifiers the d2audio? d2-814xx is a fully self-contained 4 channel digital amplifier controller system-on-chip (soc). the d2-814xx enables rapid system design for manufacturers of home theater receivers, mu lti-room distributed audio systems, and powered speakers. the d2-814xx contains a high-performance digital switching controller to play any input source on any output channel. a configurable audio signal pr ocessor provides equalization, volume control, tone control, and compression for each channel, also crossover and power limiting for powered speaker applications. the d2-814xx includes 4-channels i 2 s/left-justified inputs (16 to 24-bit, 32khz to 192khz), optional s/pdif receiver (16 to 24-bit). boot options include: self-boot from external serial rom, asynchronous sci slave boot, and serial slave boot from host ucon. please see the part number availability table for additional information on support for d2audio? soundsuite? firmware, as well as for srs labs? and dolby labs? algorithm support. features ? powerful digital audio management - reference design dependant src, routing, mixing, multiple digital audio i/o, tone control, parametric eq, compression ? reduced audio system cost for manufacturers of class-d audio amplifiers ? audio processing features enable optimized speaker performance and delivers dr amatically improved sound quality ? minimum development cost/risk/ time-to-market ? pure digital path ? superior dynamic range ? >110db snr, <0.1% thd+n ? 20hz - 20khz 0.5db frequency response complete class-d amp lifier controller soc ? digital switching controller ? flexible audio input sources ? multiple controller synchronization ? bridge and non-bridged output topologies ? stand-alone or micro-controller boot option ? 4 channels ? pb-free (rohs compliant) high-performance sound ? unique performance for each part number ? superior dynamic range ? >110 db snr, <0.1% thd+n ? 20hz-20khz 0.5db frequency response graceful protection and recovery ? complete short-circuit, overcurrent, and overvoltage fault protection pure digital path ? digital audio inputs which support i 2 s and left-justified formats with linear pcm (32khz to 192khz, 16 to 24-bit) ? digital audio input which supports s/pdif format with linear pcm (32khz to 192khz, 16 to 24-bit) multiple part offerings ? d2-81412-lr: 144-pin lqfp ? D2-81433-lr: 128-pin lqfp ? d2-81434-lr: 128-pin lqfp supporting dolby labs? technology ? d2-81435-lr: 128-pin lqfp supporting srs labs? technology data sheet march 5, 2010
2 march 5, 2010 ordering information part number (notes 2, 3, 4) part marking package (pb-free) pkg. dwg. # d2-81412-lr d2-81412-lr 144 ld lqfp q144.20x20b D2-81433-lr D2-81433-lr 128 ld lqfp q128.14x14 d2-81434-lr (note 1) d2-81434-lr 128 ld lqfp q128.14x14 d2-81435-lr (note 1) d2-81435-lr 128 ld lqfp q128.14x14 notes: 1. d2audio is obliged to confirm that ndas and/or evaluation sample licenses are in pl ace with all 3rd party ip owners and poten tial d2audio customers before the sale of product or eval uation kits which contains either a d2-81434-lr or d2-81435-lr. sale of the d2-8143 4-lr is only available to dolby laboratories licensees in good standing. sale of the d2-81435-lr is only availa ble to srs labs licensees in good standing. 2. delivery of 3rd party firmware is subjec t to prior confirmation with the 3rd party ip vendors that the oem/odm/customer is cu rrently in good standing and having the appropriate licenses in place for the respective technology. trusurround hd and trusurround hd4 are tra demarks of srs labs, inc. dolby and the double-d symbol are registered trademarks of dolby laboratories. 3. please see separate application notes fo r d2audio? soundsuite, dolby labs?, and srs l abs? firmware, register tables and signa l flow information. 4. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. d2-81412, D2-81433, d2-81434, d2-81435
3 march 5, 2010 table of contents d2-814xx architecture .................................................. 4 d2-814xx signal flow.................................................... 4 absolute maximum ratings ......................................... 5 thermal information...................................................... 5 operating conditions.................................................... 5 electrical specifications ............................................... 5 switching characteristics - serial audio port ............ 6 serial audio interface (sai ports) .......................... 6 switching characteristics - 2-wire interface .............. 7 d2-814xx 128-pin package pi nout .............. ........... ...... 8 pin definitions, 128-pin lqfp package..................... 9 pin descriptions 128-pin packag e ............ ........... ...... 11 serial audio interface (sai) pins .......................... 11 s/pdif pins ........................................................... 11 pwm pins .............................................................. 11 2-wire serial pins .................................................. 11 xgpio pins ........................................................... 11 reset and test pins .............................................. 12 crystal oscillator and pll pins ............................ 12 gpio pins............................................................. 12 system configuration pins .................................... 12 serial communications inte rface (sci) pins ........ 12 optional/reserved function pi ns ............... ........... 12 boot mode select pins .......................................... 13 timer (tio) pins .................................................... 13 pwm protection pins............................................. 13 power pins ............................................................ 13 d2-814xx 144-pin package pino ut ............... ........... .... 14 pin definitions 144-pin lqfp package ..................... 15 pin descriptions 144-pin package............................. 17 serial audio interface (sai) pins........................... 17 s/pdif pins........................................................... 18 pwm pins ............................................................. 18 2-wire serial pins .............. ................................... 18 xgpio pins........................................................... 18 reset and test pins.............................................. 18 crystal oscillator and pll pins............. ............... 18 gpio pins ............................................................ 18 system configuration pins.................................... 18 serial communications in terface (sci) pins........ 19 optional/reserved function pins.......................... 19 boot mode select pins....... ............... .............. ...... 19 timer (tio) pins.................................................... 19 pwm protection pins ............................................ 19 power pins ............................................................ 20 d2-814xx reset and boot mode s ............ .............. ...... 20 reset.......................................................................... 20 boot modes............. .............. .............. .............. ......... 20 document revision history......................................... 22 trademarks.................................................................... 23 thin plastic quad flatpack package (lqfp) ............. 24 thin plastic quad flatpack packages (lqfp) ........... 25 d2-81412, D2-81433, d2-81434, d2-81435
4 march 5, 2010 d2-814xx architecture d2-814xx signal flow the d2-814xx supports a wide variety of signal flows that are fully programmable and are reference design dependant. the d2-814xx ic is to only be used as part of a licensed reference design platform (rdp) package from d2audio corporation. the desi gner should note that each reference design platform (rdp) package has a set signal flow, which is handled by the specified firmware and associated performance level, which is determined primarily by the surrounding components used in the design. please refer to the specific d2audio digital amplifier datasheet for the design-specific signal flows and corresponding register set. power supply test serial audio interface sdin sckr lrclk mclk sclkt lrckt sdout 2 2 2 control nreset nrstout pwmsync sys bms gpio xgpio 2-wire scl sda s/pdif spdifrx spdiftx test 5 4 16 8 pll oscout xtali xtalo timer tio pssync pumplo pumphi 3 pllavdd pllagnd plldvdd plldgnd oscvdd pwmvdd pwmgnd cvdd cgnd rvdd rgnd digital signal processor sample rate conversion effects frequency response correction protection protecta protectb protectc 4 4 pwmh0 pwml0 pwmh1 pwml1 pwmh2 pwml2 pwmh3 pwml3 otsel ntrst linear interpolator pwm correction noise shaper quantizer output drive reserved serial audio interface sck0 sc0 srd0 std0 sck1 sc1 srd1 std1 3 3 pulse width modulator 4 sci sclk rxd txd figure 1. d2-814xx block diagram (144-pin package) d2-81412, D2-81433, d2-81434, d2-81435
5 march 5, 2010 . absolute maximum rati ngs thermal information supply voltage rvdd, pwmvdd . . . . . . . . . . . . . . . . -0.3v to 4.0v supply voltage cvdd, pllavdd, plldvdd, oscvdd . . . . . . . . . -0.3v to 2.4v input voltage, any input but xtali. . . . . . . . . -0.3v to rvdd + 0.3v input voltage xtali . . . . . . . . . . . . . . . . . .-0.3v to oscvdd + 0.3v input current, any pin but supplies . . . . . . . . . . . . . . . . . . . . 10ma operating conditions operating temperature (t max ) (note 5) . . . . . . . . . .-10c to +85c hermal resistance (typical, note 1) ja (c/w) jc (c/w) 128 ld lqfp airflow @ 0 . . . . . . . . . . . . . . . . . . . . 59.1 17.8 airflow @ 1m/s . . . . . . . . . . . . . . . . . 52.8 17.8 airflow @ 2m/s . . . . . . . . . . . . . . . . . 50.5 17.8 144 ld lqfp airflow @ 0 . . . . . . . . . . . . . . . . . . . . 56.5 17.6 airflow @ 1m/s . . . . . . . . . . . . . . . . . 50.9 17.6 airflow @ 2m/s . . . . . . . . . . . . . . . . . 48.9 17.6 junction temperature (t jnc ) (note 5) . . . . . . . . . . . . . . . . . . +125c storage temperature range (t stg ) (note 5) . . . . .-55c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 5. for both 128 ld lqfp and 144 ld lqfp electrical specifications parameter symbol min typ max unit pin characteristics t a = +25c, cvdd = pllavdd = plldvdd = oscvdd = 1. 8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground high level input drive voltage (note 6) v ih 2.0 - - v low level input drive voltage (note 6) v il --0.8v high level output drive voltage (note 7) iout = -pad drive v oh rvdd - 0.3 - - v low level output drive voltage (note 7) iout = +pad drive v ol --0.3v high level input drive voltage (note 8) v ihx 0.7 - oscvdd v low level input drive voltage (note 8) v ilx --0.3v high level output drive voltage oscout pin v oho plldvdd - 0.3 - - v low level output drive voltage oscout pin v olo --0.3v input leakage current i in - 10 ua input capacitance c in -9-pf output capacitance c out -9-pf power requirements typical supply currents measured at t a = +25c, pll at 300mhz, osc at 27mhz, core running at 150mhz with typical audio data traffic. minimum supply currents are measured in full power down configuration. core supply pins cvdd 1.7 1.8 1.9 v 0.01 325 ma digital i/o pad ring supply pins rvdd 3.0 3.3 3.6 v 0.01 10 ma pwm i/o pad ring supply pins pwmvdd 3.0 3.3 3.6 v 0.01 5 ma d2-81412, D2-81433, d2-81434, d2-81435
6 march 5, 2010 serial audio interface (sai ports) the d2-814xx ic contains one sai port for each pair of channels. each input can support an individually selectable sample rate from 32khz to 192khz. all digital audio inputs are 3.3v cmos logic. the sai port is designed to interface with standard digital audio components and to accept i 2 s or left-justified data formats. no te: this port is entirely independent from the reserved sai port. the reserved sai port may or may not be used in a particular design. for i 2 s format, the left channel data is read when lrck is low. for the left-justified format, the left channel data is read when lrck is high. either format requires data to be valid on the rising edge of sclk and sent msb-first on sdin with 32 bits of data per channel. each set of digital inputs runs asynchronously to the others and may accept different sample rates and formats. analog supply pins (pll) pllavdd 1.7 1.8 1.9 v 0.01 10 ma plldvdd 1.7 1.8 1.9 v 0.01 2 ma oscvdd 1.7 1.8 1.9 v 0.01 4 ma notes: 6. all input pins except xtali 7. all digital output pins 8. for xtali input overdrive operation only electrical specifications (continued) parameter symbol min typ max unit switching characteristics - serial audio port t a = +25c, cvdd = pllavdd = plldvdd = oscvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. symbol description min typ max unit t c sclk sckrx frequency - sckr0, sckr1 12.5 mhz t w sclk sckrx pulse width (high and low) - sckr0, sckr1 40 ns t s lrclk lrckrx setup to sclk rising - lrckr0, lrckr1 20 ns t h lrclk lrckrx hold from sclk rising - lrckr0, lrckr1 20 ns t s sdi sdinx setup to sclk rising - sdin0, sdin1 20 ns t h sdi sdinx hold from sclk rising - sdin0, sdin1 20 ns t d sdo sdoutx delay from sclk falling 20 ns t c sclk lrckrx sckrx sdinx sdoutx t h lrclk t s lrclk t s sdi t d sdo t h sdi t w sclk t w sclk figure 2. serial audio port timing d2-81412, D2-81433, d2-81434, d2-81435
7 march 5, 2010 figure 3. sai port data formats lrclkx sclkx serial data msb -1 -2 -3 +3 +2 +1 lsb msb -1 -2 -3 +3 +2 +1 lsb msb left channel right channel i 2 s format lrclkx left channel right channel sclkx serial data msb -1 -2 -3 +3 +2 +1 lsb msb -1 -2 -3 +3 +2 +1 lsb msb -4 left-justified -4 -1 switching characteristics - 2-wire interface t a = +25c, cvdd = pllavd = plldvdd = oscvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. symbol description min max unit fscl scl frequency 100 khz t buf bus free time between transmissions 4.7 s t wlow sclx scl clock low 4.7 s t whigh sclx scl clock high 4.0 s t s sta setup time for a (repeated) start 4.7 s t h sta start condition hold time 4.0 s t h sdax sda hold from scl falling (see note) 0 s t s sdax sda setup time to scl rising 250 ns t d sdax sda output delay time from scl falling 3.5 s t r rise time of both sda and scl 1 s t f fall time of both sda and scl 300 ns t s sto setup time for a stop condition 4.7 s note: 9. data must be held sufficient time to bridge the 300ns transition time of scl t wlow sclx sclx sdax (input) t s sta t h stax t r t f t s sdax t h sdax t s sto t buf sdax (output) t d sdax t whigh sclx figure 4. 2-wire interface timing d2-81412, D2-81433, d2-81434, d2-81435
8 march 5, 2010 d2-814xx 128-pin package pinout d2-814xx (128 ld lqfp) top view figure 5. d2-814xx pinout, 128-pin lqfp package 6 1 1 c11 s xgpio10 bms0 bms1 bms2 bms3 108 cgnd xgpio9 xgpio12 xgpio0 xgpio1 xgpio2 xgpio3 cgnd cvdd pssync pwmsync pumphi xgpio8 xgpio7 xgpio6 rvdd rgnd gpio7 xgpio11 xgpio13 l c s 8 2 1 a d s 7 2 1 1 o i t 6 2 1 0 o i t 5 2 1 t e s e r n 4 2 1 t u o t s r n 3 2 1 d n g c 2 2 1 d d v c 1 2 1 1 d r s 0 2 1 1 k c s 9 1 1 1 d t s 8 1 1 0 1 c s 7 1 1 2 1 c s 5 1 1 d n g r 4 1 1 d d v r 3 1 1 2 sys3 1 1 sys4 1 1 1 0 sys2 1 1 9 sys0 0 1 sys1 6 0 1 7 cvdd 0 1 t s r t n 5 0 1 d d v a l l p 4 0 1 d n g a l l p 3 0 1 o l a t x 2 0 1 i l a t x 1 0 1 d d v c s o 0 0 1 d d v d l l p 9 9 d n g d l l p 8 9 t u o c s o 7 9 spdiftx 1 96 pwmvdd spdifrx 2 o 95 pwmh0 txd 3 94 pwml0 rxd 4 93 pwmgnd 92 pwmvdd rvdd 5 91 pwmh1 rgnd 6 90 pwml1 sckr0 7 89 pwmgnd sdin0 8 88 pwmvdd lrckr0 9 87 pwmh2 cvdd 10 86 pwml2 cgnd 11 85 pwmgnd sckr1 12 84 pwmvdd sdin1 13 83 pwmh3 lrckr1 14 82 pwml3 mclk 15 81 pwmgnd 128-pin package 80 cgnd 79 cvdd 78 protecta0 std0 16 77 protectb0 sck0 17 76 protectc0 srd0 18 sc00 19 75 protectb1 sc01 20 74 protectc1 sc02 21 73 rgnd gpio0 22 72 rvdd cvdd 23 71 cgnd cgnd 24 70 cvdd gpio1 25 rvdd 26 69 protectb2 rgnd 27 68 protectc2 gpio2 28 gpio3 29 67 protectb3 gpio4 30 66 protectc3 gpio5 31 65 otsel gpio6 32 3 3 4 3 5 3 6 3 7 3 8 3 9 3 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 0 5 1 5 2 5 t s e t 3 5 d d v c 4 5 d n g c 5 5 6 5 7 5 d d v r 8 5 d n g r 9 5 0 6 1 6 2 6 pumplo 3 6 4 6 xgpio4 xgpio5 d2-81412, D2-81433, d2-81434, d2-81435
9 march 5, 2010 pin definitions, 128-pin lqfp package table 1. pin definitions table, 128-pin lqfp package pin number port name type description serial audio interface (sai) pins 15 mclk output master clock 7 sckr0 i/o serial audio bit clock receiver 0 9 lrckr0 i/o serial audio lef t/right clock receiver 0 8 sdin0 input serial audio data in 0 12 sckr1 i/o serial audio bit clock receiver 1 14 lrckr1 i/o serial audio lef t/right clock receiver 1 13 sdin1 input serial audio data in 1 spdif pins 1 spdiftx output s/pdif data output 2 spdifrx input s/pdif data input pwm pins 95 pwmh0 output channel 0 pwm high side output 94 pwml0 output channel 0 pwm low side output 91 pwmh1 output channel 1 pwm high side output 90 pwml1 output channel 1 pwm low side output 87 pwmh2 output channel 2 pwm high side output 86 pwml2 output channel 2 pwm low side output 83 pwmh3 output channel 3 pwm high side output 82 pwml3 output channel 3 pwm low side output 65 otsel input output topology select input 64 pwmsync i/o pwm sync 2-wire serial pins 128 scl i/o two wire serial clock 127 sda i/o two wire serial data xgpio pins 34, 35, 36, 37, 40, 43, 44, 45, 46, 47, 48 xgpio[10:0] i/o general purpose i/o 50 xgpio[11] i/o 49 xgpio[12] i/o 51 xgpio[13] i/o gpio pins 33, 32, 31, 30, 29, 28, 25, 22 gpio[7:0] i/o general purpose i/o reset and test pins 124 nreset input reset - active low 123 nrstout output reset output- active low output 105 ntrst input test reset - active low 52 test input hardware test pin crystal oscillator and pll pins 97 oscout output oscillator output to slave device 101 xtali input crystal oscillator input 102 xtalo output crystal oscillator output d2-81412, D2-81433, d2-81434, d2-81435
10 march 5, 2010 system configuration pins 109 sys0 i/o reserved for factory test 106 sys1 i/o 110 sys2 i/o 112 sys3 i/o 111 sys4 i/o serial communications interface (sci) pins 4 rxd i/o sci receive data 3 txd i/o sci transmit data reserved serial audio interface pins 16 std0 i/o reserved serial audio interface 0 tx data or gpio 17 sck0 i/o reserved serial audio interface 0 clock or gpio 18 srd0 i/o reserved serial audio interface 0 rx data or gpio 19 sc00 i/o reserved serial audio interface 0 control 0 or gpio 20 sc01 i/o reserved serial audio interface 0 control 1 or gpio 21 sc02 i/o reserved serial audio interface 0 control 2 or gpio 118 std1 i/o reserved serial audio interface 1 tx data or gpio 119 sck1 i/o reserved serial audio interface 1 clock or gpio 120 srd1 i/o reserved serial audio interface 1 rx data or gpio 117 sc10 i/o reserved serial audio interface 1 control 0 or gpio 116 sc11 i/o reserved serial audio interface 1 control 1 or gpio 115 sc12 i/o reserved serial audio interface 1 control 2 or gpio boot mode select pins 55 bms0 input boot mode select 0 56 bms1 input boot mode select 1 59 bms2 input boot mode select 2 60 bms3 input boot mode select 3 timer (tio) pins 126, 125 tio[1:0] i/o timer i/o ports 61 pumphi i/o power supply pump control, high side or gpio 62 pumplo i/o power supply pump control, low side or gpio 63 pssync i/o power supply synchronization or gpio pwm protection pins 78 protecta0 i/o pwm temperature status input, or gpio 67, 69, 75, 77 protectb[3:0] i/o pwm over current protection inputs, or gpio 66, 68, 74, 76 protectc[3:0] i/o pwm shoot through current inputs or gpio power pins 104 pllavdd power pll analog power 103 pllagnd ground pll analog ground 99 plldvdd power pll digital power 98 plldgnd ground pll digital ground 100 oscvdd power oscillator power 121, 107, 79, 70, 53, 38, 23, 10, cvdd power core power - 8 pins table 1. pin definitions table, 128-pin lqfp package (continued) pin number port name type description d2-81412, D2-81433, d2-81434, d2-81435
11 march 5, 2010 pin descriptions 128-pin package pins are 100% firmware and reference design platform (rdp) package dependent for thei r functionality. output pins have one of 3 drive strengths - 4ma, 8ma, or 16ma. these strengths are characterized by the current that the pin will source or sink at the specified output voltage level. serial audio interface (sai) pins mclk master clock output master clock output for external adc/dac components with 8ma drive strength. pin drives low on reset. mclk is also used by test hardware to mo nitor various internal clocks. sckr0 sai receiver bit clock 1 sai receiver 0 bit clock is an output when d2-814xx is a master, or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. lrckr0 sai receiver left/right clock 0 sai receiver 0 left/right audio frame clock is an output when d2-814xx is a master or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. sdin0 sai receiver serial data input 0 sai receiver 0 data input. sckr1 sai receiver bit clock 1 sai receiver 1 bit clock is an output when d2-814xx is a master, or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. lrckr1 sai receiver left/right clock 1 sai receiver 1 left/right audio frame clock is an output when d2-814xx is a master or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. sdin1 sai receiver serial data input 1 sai receiver 1 data input. s/pdif pins spdifrx s/pdif data input this pin is the s/pdif audio input and accepts a 3.3v stereo input up to 192khz. to drive this pin, appropriate buffer and/or isolation circuits may be necessary to convert the s/pdif cable input signal to clean logic levels. spdiftx s/pdif data output this pin is the s/pdif audio ou tput and drives a 3.3v stereo output up to 192khz. pwm pins pwmxh pwm high side driver outputs pwm high side driver outputs, where x is 0 to 3, with 16ma drive strength. pin drives to state determined by otsel on reset. pwmxl pwm low side driver outputs pwm low side driver outputs, where x is 0 to 3, with 16ma drive strength. pin drives low on reset. otsel output topology select input output topology select input. otsel pin state controls the pwmxh drive polarity. typically, otsel will be tied either high for active-low pwmxh fet drivers, or tied low for active-high pwmxh fet drivers. pwmsync pwm synchronization pwm synchronization port with 4ma drive. used in multi-d2- 814xx configurations to synch ronize the pwm controllers. the master d2-814xx will drive synchronization data to the slave d2-814xx(s), thus the pi n will be an output on the master d2-814xx and an input on the slave d2-814xx(s). pin floats on reset. 2-wire serial pins scl serial clock two-wire serial clock port, open drain driver with 4ma drive strength. bidirectional signal is used by both the master and slave controllers for clock signaling. sda serial data two-wire serial data port, open drain driver with 4ma drive strength. bidirectional signal used by both the master and slave controllers for data transport. xgpio pins xgpio[10:0] general purpose i/o bidirectional gpio port with 4ma driver. resets to input port. 122, 108, 80, 71, 54, 39, 24, 11 cgnd ground core ground - 8 pins 96, 92, 88, 84 pwmvdd power pwm output pin power - 4 pins 93, 89, 85, 81 pwmgnd ground pwm output pin ground - 4 pins 113, 72, 57, 41, 26, 5 rvdd power digital pad ring power - 6 pins 114, 73, 58, 42, 27, 6 rgnd ground digital pad ring ground - 6 pins table 1. pin definitions table, 128-pin lqfp package (continued) pin number port name type description d2-81412, D2-81433, d2-81434, d2-81435
12 march 5, 2010 xgpio[11] general purpose i/o bidirectional gpio port with 4ma driver. resets to input port. xgpio[12] general purpose i/o bidirectional gpio port with 4ma driver. resets to input port. xgpio[13] general purpose i/o bidirectional gpio port with 4ma driver. resets to input port. reset and test pins nreset system reset input active low reset input with hysteresis. low level activates system level reset, initializing all internal logic and program operations. system latches boot mode selection on the irq input pins on the rising edge. nrstout system reset output active low reset output with 4ma driver. pin drives low on any of por output, 3.3v brown out detector, 1.8v brown out detector. test test mode input hardware test mode control. for d2audio usage only. must be tied low. ntrst test reset input active low test port reset. low level activates test reset, initializing test hardware. mu st be driven low with nreset. crystal oscillator and pll pins oscout oscillator output analog oscillator output to slave d2-814xx devices. on reset, oscout drives a buffered version of the crystal oscillator signal from the xtali pin. may be turned off by program control. xtali crystal oscillator input crystal oscillator analog input port. an external clock source would be driven into the this port. in multi-d2-814xx systems, the oscout from the master d2-814xx would drive the xtali pin. xtalo crystal oscillator output crystal oscillator analog output port. when using an external clock source, this pin must be open. gpio pins gpio[7:0] general purpose i/o bidirectional gpio ports with 4ma driver. resets to input ports. system configuration pins sys0 system configuration data 0 reserved for factory test. tie low with 10k resistor. sys1 system configuration data 1 reserved for factory test. tie high with 10k resistor. sys2 system configuration data 2 reserved for factory test. tie high with 10k resistor. sys3 system configuration data 3 reserved for factory test. tie high with 10k resistor. sys4 system configuration data 4 reserved for factory test. tie high with 10k resistor. serial communications interface (sci) pins rxd receive data serial communications receiver data with 4ma drive. resets to input port. may be configured to gpio. txd transmit data serial communications transmitter data with 4ma drive. resets to input port. may be configured to gpio. optional/reserved function pins sck0 reserved serial audio interface 0 serial clock serial audio interface 0 serial clock port with 4ma driver and hysteresis receiver. resets to input port. may be configured as gpio. sc00-sc02 reserved serial audio interface 0 serial control 0 serial control port with 4ma driver. resets to input port. may be configured as gpio. std0 reserved serial audio interface 0 serial transmit data serial audio interface 0 serial transmit data port with 4ma driver. resets to input port. may be configured as gpio. srd0 reserved serial audio interface 0 serial receive data serial audio interface 0 serial receive data port with 4ma driver. resets to input port. may be configured as gpio. sck1 reserved serial audio interface 1 serial clock serial audio interface 1 serial clock port with 4ma driver and hysteresis receiver. resets to input port. may be configured as gpio. sc10-sc12 reserved serial audio interface 1 serial control serial audio interface 1 serial control port with 4ma driver. resets to input port. may be configured as gpio. std1 reserved serial audio interface 1 serial transmit data serial audio interface 1 serial transmit data port with 4ma driver. resets to input port. may be configured as gpio. srd1 reserved serial audio interface 1 serial receive data serial audio interface 1 serial receive data port with 4ma driver. resets to input port. may be configured as gpio. d2-81412, D2-81433, d2-81434, d2-81435
13 march 5, 2010 boot mode select pins bms[3:0] boot mode select inputs external boot mode select inputs. on nreset deassertion, these pins provide the boot mode selection. timer (tio) pins tio[1:0] timer timer i/o ports with 4ma driver. may be configured as gpio. pumphi power supp ly pump high high side power supply pump output with 16ma driver. may be configured as gpio. drives low on reset. provides control means for operating an external switching power supply. pumplo power supply pump low low side power supply pump output with 16ma driver. may be configured as gpio. drives lo w on reset. provides control means for operating an external switching power supply. pssync power supply synchronization switching power supply synchronization signal with 16ma driver. may be configured as gpio. resets to input port. pwm protection pins protecta0 pwm temperat ure protection input pwm temperature protection in put with hysteresis. may be configured as gpio. in this instance, the gpio pin has a 4ma driver. protectb[3:0] pwm overcurrent protection inputs pwm overcurrent protection input s with hysteresis. may be configured as gpio. in this instance, the gpio pins each have a 4ma driver. each pwmocp input is associated with the corresponding pwm driver channel. protectc[3:0] pwm shoot-through current protection pwm shoot-through-current protection inputs with hysteresis. in this instance, the gpio pins each have a 4ma driver. may be configured as gpio. each pwmstc input is associated with the corresponding pwm driver channel. power pins pllavdd/pllagnd pll analog power and ground pll analog supply/return. this 1.8v supply is used for the jitter critical sections of the pll. plldvdd/plldgnd pll digital power and ground pll digital supply/return. this 1.8v supply is used for the ?dirty? sections of the pll, and provides the pad supplies for all of the analog pads. note that plldgnd and cgnd are connected through the substrate. oscvdd oscillator power oscillator supply. this 1.8v supply is used for the crystal oscillator and oscillator bias circuits only. cvdd/cgnd core power and ground core supply/return. this 1.8v supply is used in the chip interior logic and pad ring interfaces. there are 8 core supply pad pairs internally connected around the pad ring. pwmvdd/pwmgnd pwm driver power and ground pwm i/o pad driver supply/return. this 3.3v supply is used for the pwm pad drivers only. there are 4 pwm internally connected supply pairs, one for each pwm data channel. rvdd/rgnd pad ring power and ground ring i/o pad driver supply/return. this 3.3v supply is used for all the digital i/o pad drivers and receivers except for the pwm and analog pads. there are 6 ring supply pairs internally connected around the pad ring. d2-81412, D2-81433, d2-81434, d2-81435
14 march 5, 2010 d2-814xx 144-pin package pinout d2-814xx (144 ld lqfp) top view figure 6. d2-814xx pinout, 144-pin lqfp package l c s 4 4 1 a d s 3 4 1 2 o i t 2 4 1 1 o i t 1 4 1 0 o i t 0 4 1 t e s e r n 9 3 1 t u o t s r n 8 3 1 d n c 7 g 3 1 d d c v 6 3 1 srd1 5 3 1 sck1 4 3 1 std1 3 3 1 sc10 2 3 1 sc11 1 3 1 sc12 0 3 1 d n g r 9 2 1 d d v r 8 2 1 sys3 7 2 1 sys4 6 2 1 sys2 5 2 1 sys0 4 2 1 d n g c 3 2 1 d d v c 2 2 1 sys1 1 2 1 ntrst 0 2 1 d d v a l l p 9 1 1 d n g a l l p 8 1 1 d n g c s o 7 1 1 o l a t x 6 1 1 i l a t x 5 1 1 d d v c s o 4 1 1 c n 3 1 1 c n 2 1 1 d d v d l l p 1 1 1 d n g d l l p 0 1 1 t u o c s o 9 0 1 spdiftx 1 108 pwmvdd spdifrx 2 o 107 pwmh0 106 pwml0 txd 3 rxd 4 105 pwmgnd sclk 5 104 pwmvdd rvdd 6 103 pwmh1 rgnd 7 102 pwml1 sckr0 8 101 pwmgnd sdin0 9 100 pwmvdd lrckr0 10 99 pwmh2 cvdd 11 98 pwml2 cgnd 12 97 pwmgnd sckr1 13 96 pwmvdd sdin1 14 95 pwmh3 lrckr1 15 94 pwml3 mclk 16 93 pwmgnd 92 cgnd 144-pin package 91 cvdd 90 protecta0 std0 20 89 protectb0 sck0 21 88 protectc0 srd0 22 87 protecta1 sc00 23 86 protectb1 sc01 24 85 protectc1 sc02 25 84 rgnd gpio0 26 83 rvdd cvdd 27 82 cgnd cgnd 28 81 cvdd gpio1 29 80 protecta2 rvdd 30 79 protectb2 rgnd 31 78 protectc2 gpio2 32 77 protecta3 gpio3 33 76 protectb3 gpio4 34 75 protectc3 gpio5 35 74 otsel gpio6 36 73 nc 7 3 7 o i p g 8 3 5 1 o i p g x 9 3 4 1 o i p g x 0 4 0 1 o i p g x 1 4 9 o i p g x 2 4 8 o i p g x 3 4 7 o i p g x 4 4 d d v c 5 4 d n g c 6 4 6 o i p g x 7 4 d d v r 8 4 d n g r 9 4 5 o i p g x 0 5 4 o i p g x 1 5 3 o i p g x 2 5 2 o i p g x 3 5 1 o i p g x 4 5 0 o i p g x 5 5 2 1 o i p g x 6 5 1 1 o i p g x 7 5 3 1 o i p g x 8 5 t s e t 9 5 d d v c 0 6 d n g c 1 6 0 s m b 2 6 1 s m b 3 6 d d v r 4 6 d n g r 5 6 2 s m b 6 6 3 s m b 7 6 pumphi 0 7 nc 1 7 c n 9 6 pssync 72 pwmsync 68 pumplo sckt 17 sdout 18 lrckt 19 d2-81412, D2-81433, d2-81434, d2-81435
15 march 5, 2010 pin definitions 144-pin lqfp package table 2. pin definitions, 144-pin lqfp package pin number port name type description serial audio interface (sai) pins 16 mclk output master clock output 8 sckr0 i/o serial audio input 0 clock receiver 10 lrckr0 i/o serial audio input 0 left/right clock receiver 9 sdin0 input serial audio input 0 data 13 sckr1 i/o serial audio input clock 1 receiver 15 lrckr1 i/o serial audio input 1 left/right clock receiver 14 sdin1 input serial audio input 1 data 17 sckt i/o serial audio output clock transmit 19 lrckt i/o serial audio output left/right clock transmit 18 sdout output serial audio output s/pdif 1 spdiftx output s/pdif data out 2 spdifrx input s/pdif data in pwm pins 107 pwmh0 output channel 0 pwm high side output 106 pwml0 output channel 0 pwm low side output 103 pwmh1 output channel 1 pwm high side output 102 pwml1 output channel 1 pwm low side output 99 pwmh2 output channel 2 pwm high side output 98 pwml2 output channel 2 pwm low side output 95 pwmh3 output channel 3 pwm high side output 94 pwml3 output channel 3 pwm low side output 74 otsel input output topology select input 72 pwmsync i/o pwm sync 2-wire serial pins 144 scl i/o two wire serial clock 143 sda i/o two wire serial data xgpio pins 43, 46, 49, 50, 51, 52, 53, 54 xgpio[7:0] i/o general purpose i/o 38, 39, 57, 55, 56, 40, 41, 42 xgpio[15:8] i/o reset and test pins 139 nreset input reset - active low 138 nrstout output reset output- active low output 120 ntrst input test reset - active low 58 test input hardware test pin crystal oscillator and pll pins 109 oscout output oscillator output to slave device d2-81412, D2-81433, d2-81434, d2-81435
16 march 5, 2010 115 xtali input crystal oscillator input 116 xtalo output crystal oscillator output gpio pins 37, 36, 35, 34, 33, 32, 29, 26 gpio[7:0] i/o general purpose i/o system configuration pins 124 sys0 i/o reserved for factory test 121 sys1 i/o 125 sys2 i/o 127 sys3 i/o 126 sys4 i/o serial communications interface (sci) pins 5 sclk i/o sci clock 4 rxd i/o sci receive data 3 txd i/o sci transmit data reserved serial audio interface pins 20 std0 i/o reserved serial audio interface 0 tx data or gpio 21 sck0 i/o reserved serial audio interface 0 clock or gpio 22 srd0 i/o reserved serial audio interface 0 rx data or gpio 23 sc00 i/o reserved serial audio interface 0 control 0 or gpio 24 sc01 i/o reserved serial audio interface 0 control 1 or gpio 25 sc02 i/o reserved serial audio interface 0 control 2 or gpio 133 std1 i/o reserved serial audio interface 1 tx data or gpio 134 sck1 i/o reserved serial audio interface 1 clock or gpio 135 srd1 i/o reserved serial audio interface 1 rx data or gpio 132 sc10 i/o reserved serial audio interface 1 control 0 or gpio 131 sc11 i/o reserved serial audio interface 1 control 1 or gpio 130 sc12 i/o reserved serial audio interface 1 control 2 or gpio boot mode select pins 61 bms0 input boot mode select 0 62 bms1 input boot mode select 1 65 bms2 input boot mode select 2 66 bms3 input boot mode select 3 timer (tio) pins 142, 141, 140 tio[2:0] i/o timer i/o ports 67 pumphi i/o power supply pump control, high side or gpio 68 pumplo i/o power supply pump control, low side or gpio 69 pssync i/o power supply synchronization or gpio pwm protection pins 77, 80, 87, 90 protecta[3:0] i/o pwm temperature status input, or gpio table 2. pin definitions, 144-pin lqfp package (continued) pin number port name type description d2-81412, D2-81433, d2-81434, d2-81435
17 march 5, 2010 pin descriptions 144-pin package pins are 100% firmware and reference design platform (rdp) package dependent for their functionality. output pins have one of 3 drive strengths - 4ma, 8ma, or 16ma. these strengths are characterized by the current that the pin will source or sink at the specified output voltage level. serial audio interface (sai) pins mclk master clock output master clock output for external adc/dac components with 8ma drive strength. pin drives low on reset. mclk is also used by test hardware to mo nitor various internal clocks. sckr0 sai receiver bit clock 1 sai receiver 0 bit clock is an output when d2-814xx is a master, or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. lrckr0 sai receiver left/right clock 0 sai receiver 0 left/right audio frame clock is an output when d2-814xx is a master or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. sdin0 sai receiver serial data input 0 sai receiver 0 data input. sckr1 sai receiver bit clock 1 sai receiver 1 bit clock is an output when d2-814xx is a master, or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. lrckr1 sai receiver left/right clock 1 sai receiver 1 left/right audio frame clock is an output when d2-814xx is a master or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. input has hysteresis. sdin1 sai receiver serial data input 1 sai receiver 1 data input. sckt sai transmitter bit clock sai transmitter bit clock is an output when d2-814xx is a master, or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. sckt is used to monitor the 3.3v brownout detector during the por hardware test. 76, 79, 86, 89 protectb[3:0] i/o pwm over current protection inputs, or gpio. 75, 78, 85, 88 protectc[3:0] i/o pwm shoot through current inputs or gpio. power pins 119 pllavdd power pll analog power 118 pllagnd ground pll analog ground 111 plldvdd power pll digital power 110 plldgnd ground pll digital ground 114 oscvdd power oscillator power 117 oscgnd ground oscillator ground 11, 27, 44, 59, 81, 91, 122, 136 cvdd power core power - 8 pins 12, 28, 45, 60, 82, 92, 123, 137 cgnd ground core ground - 8 pins 96, 100, 104, 108 pwmvdd power pwm output pin power - 4 pins 93,97,101,105 pwmgnd ground pwm output pin ground.- 4 pins 6, 30, 47, 63, 83, 128 rvdd power digital pad ring power - 6 pins 7, 31, 48, 64, 84, 129 rgnd ground digital pad ring ground- 6 pins no connect pins 70, 71, 73, 112, 113 nc no connect, leave pin floating table 2. pin definitions, 144-pin lqfp package (continued) pin number port name type description d2-81412, D2-81433, d2-81434, d2-81435
18 march 5, 2010 lrckt sai transmitter left/right clock sai transmitter left/right audio frame clock is an output when d2-814xx is a master, or an input when d2-814xx is a slave. defaults to an input on reset. output has 4ma drive strength. lrckt is used to monitor the 1.8v brown out detector during the por hardware test. lrckt is used to monitor pll lock during the pll hardware test. sdout serial data output sai transmitter data output with 4ma drive strength. pin drives low on reset. s/pdif pins spdifrx s/pdif data input this pin is the s/pdif audio input and accepts a 3.3v stereo input up to 192khz. to drive this pin, appropriate buffer and/or isolation circuits may be necessary to convert the s/pdif cable input signal to clean logic levels. spdiftx s/pdif data output this pin is the s/pdif audio output and drives a 3.3v stereo output up to 192khz. pwm pins pwmxh pwm high side driver outputs pwm high side driver outputs, where x is 0 to 3, with 16ma drive strength. pin dr ives to state determined by otsel on reset. pwmxl pwm low side driver outputs pwm low side driver outputs, where x is 0 to 3, with 16ma drive strength. pin dr ives low on reset. otsel output topology select input output topology select input. otsel pin state controls the pwmxh drive polarity. typically, otsel will be tied either high for active-low pwmxh fet drivers, or tied low for active-high pwmxh fet drivers. pwmsync pwm synchronization pwm synchronization port with 4ma drive. used in multi-d2-814xx configurations to synchronize the pwm controllers. the master d2-814xx will drive synchronization data to the slave d2-814xx(s), thus the pin will be an output on the master d2-814xx and an input on the slave d2- 814xx(s). pin floats on reset. 2-wire serial pins scl serial clock two-wire serial clock port, open drain driver with 4ma drive strength. bidirectional signal is used by both the master and slave controllers for clock signaling. sda serial data two-wire serial data port, open drain driver with 4ma drive strength. bidirectional signal used by both the master and slave controllers for data transport. xgpio pins xgpio[15:0] extended general purpose i/o bidirectional gpio port with 4ma driver. resets to input port. reset and test pins nreset system reset input active low reset input with hysteresis. low level activates system level reset, in itializing all internal logic and program operations. system latches boot mode selection on the irq input pins on the rising edge. nrstout system reset output active low reset output with 4ma driver. pin drives low on any of por output, 3.3v brown out detector, 1.8v brown out detector. test test mode input hardware test mode control. for d2audio usage only. must be tied low. ntrst test reset input active low test port reset. lo w level activates test reset, initializing test hardware. mu st be driven low with nreset. crystal oscillator and pll pins oscout oscillator output analog oscillator output to sl ave d2-814xx devices. on reset, oscout drives a buffered version of the crystal oscillator signal from the xtali pin. may be turned off by program control. xtali crystal oscillator input crystal oscillator analog input port. an external clock source would be driven into the this port. in multi-d2-814xx systems, the oscout from t he master d2-814xx would drive the xtali pin. xtalo crystal oscillator output crystal oscillator analog output port. when using an external clock source, this pin must be open. gpio pins gpio[7:0] general purpose i/o bidirectional gpio ports with 4ma driver. resets to input ports. system configuration pins sys0 system configuration data 0 reserved for factory test. tie low with 10k resistor. d2-81412, D2-81433, d2-81434, d2-81435
19 march 5, 2010 sys1 system configuration data 1 reserved for factory test. tie high with 10k resistor. sys2 system configuration data 2 reserved for factory test. tie high with 10k resistor. sys3 system configuration data 3 reserved for factory test. tie high with 10k resistor. sys4 system configuration data 4 reserved for factory test. tie high with 10k resistor. serial communications interface (sci) pins sclk serial clock serial communications clock with 4ma drive and hysteresis on input. resets to input port. may be configured to gpio. rxd receive data serial communications receiver data with 4ma drive. resets to input port. may be configured to gpio. txd transmit data serial communications transmitter data with 4ma drive. resets to input port. may be configured to gpio. optional/reserved function pins sck0 reserved serial audio interface 0 serial clock serial audio interface 0 serial clock port with 4ma driver and hysteresis receiver. resets to input port. may be configured as gpio. sc00-sc02 reserved serial audio interface 0 serial control serial audio interface 0 serial control port with 4ma driver. resets to input port. may be configured as gpio. std0 reserved serial audio interface 0 serial transmit data serial audio interface 0 serial transmit data port with 4ma driver. resets to input port. may be configured as gpio. srd0 reserved serial audio interface 0 serial receive data serial audio interface 0 serial receive data port with 4ma driver. resets to input port. may be configured as gpio. sck1 reserved serial audio interface 1 serial clock serial audio interface 1 serial clock port with 4ma driver and hysteresis receiver. resets to input port. may be configured as gpio. sc10-sc12 reserved serial audio interface 1 serial control serial audio interface 1 serial control port with 4ma driver. resets to input port. may be configured as gpio. std1 reserved serial audio interface 1 serial transmit data serial audio interface 1 serial transmit data port with 4ma driver. resets to input port. may be configured as gpio. srd1 reserved serial audio interface 1 serial receive data serial audio interface 1 serial receive data port with 4ma driver. resets to input port. may be configured as gpio. boot mode select pins bms[3:0] boot mode select inputs external boot mode select inputs. on nreset deassertion, these pins provide the boot mode selection. timer (tio) pins tio[2:0] timer timer i/o ports with 4ma driver. may be configured as gpio. pumphi power supply pump high high side power supply pump output with 16ma driver. may be configured as gpio. drives low on reset. provides control means for operating an external switching power supply. pumplo power supply pump low low side power supply pump output with 16ma driver. may be configured as gpio. drives low on reset. provides control means for operating an external switching power supply. pssync power supply synchronization switching power supply synchronization signal with 16ma driver. may be configured as gpio. resets to input port. pwm protection pins protecta[3:0] pwm temper ature protection inputs pwm temperature protection inputs with hysteresis. may be configured as gpio. in this instance, the gpio pins each have a 4ma driver. each pwmtemp input is associated with the corresponding pwm driver channel. protectb[3:0] pwm overcurre nt protection inputs pwm overcurrent protection inputs with hysteresis. may be configured as gpio. in this instance, the gpio pins each have a 4ma driver. each pwmocp input is associated with the corresponding pwm driver channel. protectc[3:0] pwm shoot-through current protection pwm shoot-through-current protection inputs with hysteresis. may be configured as gpio. in this instance, the gpio pins each have a 4ma driver. each pwmstc input is associated with the corresponding pwm driver channel. d2-81412, D2-81433, d2-81434, d2-81435
20 march 5, 2010 power pins pllavdd/pllagnd pll analog power and ground pll analog supply/return. this 1.8v supply is used for the jitter critical sections of the pll. plldvdd/plldgnd pll digital power and ground pll digital supply/return. this 1.8v supply is used for the ?dirty? sections of the pll, and provides the pad supplies for all of the analog pads. note that plldgnd and cgnd are connected through the substrate. oscvdd/oscgnd oscillator power and ground oscillator supply/return. this 1.8v supply is used for the crystal oscillator and oscillator bias circuits only. cvdd/cgnd core power and ground core supply/return. this 1.8v supply is used in the chip interior logic and pad ring interfaces. there are 8 core supply pad pairs internally connected around the pad ring. pwmvdd/pwmgnd pwm driver power and ground pwm i/o pad driver supply/return. this 3.3v supply is used for the pwm pad drivers only. there are 4 pwm internally connected supply pairs, one for each pwm data channel. rvdd/rgnd pad ring power and ground ring i/o pad driver supply/return. this 3.3v supply is used for all the digital i/o pad drivers and receivers except for the pwm and analog pads. there are 6 ring supply pairs internally connected around the pad ring. d2-814xx reset and boot modes reset d2-814xx has a two reset inpu ts - the nreset and ntrst input pins. the nreset input pin is effectively a power-on system reset. all inte rnal state logic, except internal test hardware, is initiali zed by nreset. while re set is active the system is held in the reset cond ition. the reset condition is defined as all internal reset signals being active, the crystal oscillator is running, and the pll disabled. the ntrst input resets internal factory test hardware only. to assure proper system initia lization, the ntrst input pin must be asserted along with nreset. boot modes the boot mode is determined by the bms[3:0] pin inputs. the bms[3:0] pin state is la tched on the deassertion of system reset. it is expected that the application board will have pull-ups in the bms[3:0] pi ns, so that the desired boot mode is selected by default. table 4 defines the boot modes. the interface speed s pecification is the speed at which the interface is configured to oper ate by the boot code. for the selection where the interface speed is ?per master?, the interface must operate withi n the requirements of the selected interface specification. for example, the eeprom boot speed with 2-wire interface is 400khz. table 3. power on reset timing details symbol description min typ max unit t-1.8vgood valid 1.8v power before nreset release 10 ns t-3.3vgood valid 3.3v power before nreset release 10 ns tbmssu boot mode select (bms[3:0]) setup 10 ns tbmshld boot mode select (bms[3:0]) hold 0ns table 4. boot modes mode bms[3:0] m/s interface speed description 0 0000 reserved 1 0001 m 400kb/s rom on 2-wire 0 port 2 0010 s 384kb/s fast asynchronous sci slave boot (ex: d2-814xx to d2-814xx) 3 0011 s per master spi slave 7 0111 m 384kb/s 2-wire rom on gpio port (scl=gpio7, sda = gpio6) 8 1000 reserved 9 1001 reserved a 1010 reserved b 1011 reserved c 1100 s per master 2-wire slave boot from micro, address = 1000100x d 1101 reserved e 1110 reserved f 1111 reserved xxxx tbmshld tbmssu t-3.3vgood t-1.8vgood 0ns 50ns 100ns 150ns 200ns 1.8v -powergood 3.3v -powergood nreset bms[3:0] figure 7. power on reset timing d2-81412, D2-81433, d2-81434, d2-81435
21 march 5, 2010 table 5. external host boot timing details symbol description min typ max unit tbmssu boot mode select (bms[3:0]) setup 10 ns tbmshld boot mode select (bms[3:0]) hold 0ns textbootrdy 2-wire external source ready to boot 2400000 ns table 6. 2-wire eeprom boot timing details symbol description min typ max unit teeboot 2-wire ee boot delay 2650000 ns tbmssu boot mode select (bms[3:0]) setup 10 ns tbmshld boot mode select (bms[3:0]) hold 0ns 0000 textbootrdy tbmshold tbmssu 0us 2500us bms[3:0] nreset scl1 sda1 figure 8. external host boot timing 0100 teeboot tbmshold tbmssu 0us 2500us nreset bms[3:0] scl0 sda0 figure 9. 2-wire eeprom boot timing d2-81412, D2-81433, d2-81434, d2-81435
22 march 5, 2010 document revision history 07/25/05 revision 0.0.1 - first internal release. created new data sheet template, updated product features, incl uded new drawings of 128-pin package, included new 128-pin pinou t and pin name descriptions. 08/12/05 revision 0.0.2 - second internal release. updated product features, included new drawi ngs of 128-pin/144-pin package, included new 144-pin pinout and pin name descriptio ns. 08/15/05 revision 0.0.3 - third internal release. updated pins in 128-pin/144-pin package drawings, eliminated signal flow diagram, added 2 part numbers. 08/17/05 revision 0.0.4 - fourth internal release. updated ic image on master pages, added section 8.1 ?0? performance option, renamed document, updated cover page. 09/14/05 revision 0.0.5 - fifth internal release. updated all 128/144 package pinout tables and descriptions, removed waveforms, added block diagram, updated cover page. 10/20/05 revision 1.0.0 - first external release. updated cover page, updated block diagram serial audio interfac e, updated otsel pin desc ription, added 2-wire interface and ser ial audio port sections, added firmware and reference de sign disclaimers, updated part numbers. 12/6/05 revision 1.0.1 updated sys0 pin from tie-high to tie-low. 12/22/05 revision 1.0.2 corrected cover page feature set descriptions, corr ected available part numbers in ordering table. 1/31/06 revision 1.0.3 changed 128-pin package pinouts in figure 5 on page 8, and table 1 on page 9. 2/7/06 revision 1.0.4 changed text on cover page regarding valid boot modes. updated figure 1 on page 4 to relabel the seri al audio block to serial au dio interface block. renamed serial audio interface block to be reserved seri al audio interface block. updated text in ?d2-814xx signal flow? on page 4. changed ?module? to ?ic? in ?serial audio interface (sai ports)? on page 6. updated text in table 1 on page 9 to change ?serial au dio (sai) pins? to be ?serial audio interface (sai) pins?. updated text in tabl e 1 on the following page to ch ange ?serial audio interface pins? to be ?reserved serial audio interface pins? in both header and pin description sections. changed title in ?serial audio interface (sai) pins? on page 11 from ?serial audio (sai) pins? to be ?serial audio interf ace (sai) pins?. changed spdif to s/pdif in section ?serial audio interface (sai) p ins? on page 11. deleted ?or nreset active low? from ?reset and test pins? on p age 12 and in ?reset and test pins? on page 18 from the nrstout pin description. changed the title in ?o ptional/reserved function pins? on page 12 from ?optional function pins ? to ?optional/reserv ed function pins?. changed the pin descriptions in this section to now have a ?reserved? in fron t. changed text in ?pwm protection pins? on page 13 on all pin descriptions. relabeled pi n ?sdo? to ?sdout? in figure 6 on page 14, in table 2 on page 15 as well as in ?serial audio interfa ce (sai) pins? on page 17. 2/8/06 revision 1.0.5 changed all related text, pin descriptions and pi nout drawings for ctrl0, ctrl1, ctrl2, ctrl3. ctrl0 is now pumphi. ctrl1 is no w pumplo. ctrl2 is now pssync. ctrl3 is now pwmsync. 2/20/06 revision 1.0.6 added junction temperature to table 1, ?absolute maximum ratings,? on page 5 in addition to note 1 on operating temperature, stor age temperature and storage temperature. added table 4, ?thermal characteristics,? on page 6 which shows theta j a and j c values for 128-pin and 144-pin lqfp packages. 3/27/06 revision 1.1.1 updated theta j a and j c values for 128-pin and 144-pin lqfp packages in table 4, ?thermal characteristics,? on page 6. 7/17/06 revision 1.1.2 changed core supply pins cvdd from 300 ma to 325 ma in table 3, ?power requirements,? on page 6 updated environment category in section , ?ic part numbering scheme,? on page 25 swapped theta j a and j c values for 128-pin and 144-pin lqfp packages in table 4, ?thermal characteristics,? on page 6 11/29/06 revision 1.1.3 added [3:0] vector to table 4, ?boot modes,? on page 20 added timing details table 3, ?power on reset timing details,? on page 20, table 5, ?external host boot timing details,? on page 21, table 6, ?2-wire eeprom boot timing details,? on page 21 d2-81412, D2-81433, d2-81434, d2-81435
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com march 5, 2010 trademarks d2?, d2a?, d2audio?, d2audio 360sound?, d2audio accumatr ix?, d2audio acoustical speaker detect?, d2audio afrc (automatic frequency response compensa tion)?, d2audio armc (automatic r oom mode correction)?, d2audio audio canvas?, d2audio audioalign?, d2audio canvas?, d2audio canvas 2.0?, d2audio canvas ii?, d2audio clearvoice?, d2audio deepbass?, d2audio digitaleq?, d2 audio electrical speaker detect?, d2 audio hilo?, d2audi o leo (listenting environment optimization)?, d2audio leoxpc?, d2audio load monitor?, d2audio mono2stereo?, d2audio multi-crossover digital bass management?, d2audio multimix?, d2audio multi-mix?, d2audio page-in?, d2audio sound pressure normalization?, d2audio soundsuite?, d2audio speaker dete ct?, d2audio speaker distance?, d2audio speaker eq (speq)?, d2audio speaker fingerprint?, d2audio speaker impedance?, d2audio speaker polarity?, d2audio widesound?, digital audio engine? and dae-3? are trademarks of d2audio corporation. audistry? by dolby, dolby headphone?, dolby pro logic ii, dolby pro logic ii/iix?, dolb y pro logic ii?, dolby virtual speaker?, and surround ex? are trademarks of dolby laboratorie s licensing corporation. audyssey 2eq?, audyssey eq?, audyssey multeq pro?, audyssey multeq xt? and audyssey multeq? are trademarkss of audyssey laboratories, inc. bbe? is a trademark of bbe sound, inc. dts neo:6? is a trademark of digital theater systems, inc. logic 7? is a trademark of harman international industries, incor porated. microsoft?, windows? xp, windows? 2000 are trademarks of microsoft corporation. srs definition?, srs dialog clarity?, srs focus?, srs headphone 360?, srs trubass?, srs trusurround hd?, srs trusurround hd4?, srs trusurround xt hd/hd4?, srs trusurround xt?, srs trusurround?, srs wow hd? and srs wow? are trademarks of srs labratories, inc. thx adaptive de-correlation?, thx advanced speaker array (asa)?, thx bass management with bass peak limiter?, thx boundary gain compensation (bgc)?, thx cinema re-eq?, thx? ultra2? and thx? select ? are trademarks of thx ltd. added timing sequence figures fi gure 7, ?power on reset timing,? on page 20, figur e 8, ?external host boot timing,? on page 21, figure 9, ?2-wire eeprom boot timing,? on page 21 10/4/07 revision 1.1.4 added new part numbers (d2-81434-lr and d2-81435-lr) on page 1 and pages 32, 33 revised part descriptions to include new part numbers 3/5/10 revision fn6786.0 converted to intersil format. assigned file number fn6786. rev 0 - first release with this file num ber. removed part numbering scheme and replaced available parts with ordering information table. document revision history (continued) d2-81412, D2-81433, d2-81434, d2-81435
24 march 5, 2010 d2-81412, D2-81433, d2-81434, d2-81435 thin plastic quad fl atpack package (lqfp) d d1 z 1 t 144 pin 1 corner u e1 e 0.2 y t-u z h e/2 b/1 c b c/1 0.2 h t-u z gg y 0.08 detail f e y 0.08 m y t-u z seating plane 144x b 140x section g-g detail f 4x 36 73 108 109 4x base metal plating aa2 02 01 r1 r2 l1 0.25 gauge s 03 plane a1 0.05 l q144.20x20b 144 lead thin plastic quad flatpack package symbol millimeters notes min nom max a- -1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 4 b1 0.17 0.20 0.23 c 0.09 - 0.20 c1 0.09 - 0.16 d 22 bsc d1 20 bsc 3 e 22 bsc e1 20 bsc 3 l 0.45 0.60 0.75 l1 1.00 ref r1 0.08 - - r2 0.08 - 0.20 s0.20 - - 0 3.5 7.0 10 - - 2 11 12 13 3 11 12 13 n 128 5 e0.50 bsc rev. 0 9/08 notes: 1. dimensions are in millimeters. dimensions in ( ) for reference only. 2. dimensioning and tolerancing conform to amse y14.5m-1994. 3. dimensions d1 and e1 are excluding mold protrusion. allowable protrusion is 0.25mm per side. dimensions d1 and e1 are inclusive of mold mismatch and determined by datum plane h. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall not caus e the lead width to exceed the maximum b dimension by more than 0.08mm. dambar cannot be located at the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. 5. n is total number of the lead terminals.
25 march 5, 2010 d2-81412, D2-81433, d2-81434, d2-81435 thin plastic quad fl atpack packages (lqfp) d e d1 e1 e 128x b l (l1) a1 a2 a r2 r1 s 02 0 3 b1 c1 c b 1 32 33 64 65 96 97 128 seating plane y 0.080 y detail f detail f 124x 0.25 gauge plating 0.05 0.07 y t-u z u t 0.2 h t-u z 4x 0.2 y t-u z 4x h plane 01 0 pin 1 m q128.14x14 128 lead thin plastic quad flatpack package .4 mm pitch symbol millimeters notes min nom max a - 1.60 - a1 0.05 0.15 - a2 1.35 1.40 1.45 - b 0.13 0.16 0.23 4 b1 0.13 - 0.19 - c 0.09 - 0.20 - c1 0.09 - 0.16 - d16 bsc- d1 14 bsc 3 e16 bsc- e1 14 bsc 3 l 0.45 0.60 0.75 - l1 1.00 ref - r1 0.08 - - - r2 0.08 - 0.20 - s0.20--- 003.57- 010--- 02 11 12 13 - 03 11 12 13 - n 128 - e0.40 bsc- rev. 0 8/08 notes: 1. dimensions are in millimeters. dimensions in ( ) for refer- ence only. 2. dimensions and tolerances per amsey14.5m-1994. 3. dimensions d1 and e1 are excluding mold protrusion. al- lowable protrusion is 0.25 per side. dimensions d1 and e1 are exclusive of mold mismat ch and determined by datum plane h. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall not ca use the lead width to exceed the maximum b dimension by more than 0.08mm. dambar cannot be located at the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm.

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